Leaked slides make reference to the AMD Zen 5 microarchitecture.

A few slides from AMD's internal presentation were leaked online by Moore's Law is Dead, revealing details about the alleged next-generation "Zen 5" microarchitecture. Internally, the high-performance version of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores is codenamed "Eldora." These CCDs will be used in either AMD's Ryzen "Granite Ridge" desktop processors or EPYC "Turin" server processors. The cores may also be included in the company's next-generation mobile processors as part of heterogeneous CCXs (CPU core complex), alongside "Zen 5c" low-power cores.

In general terms, AMD claims that "Zen 5" will bring a 10% to 15% increase in IPC (Instructions Per Cycle) compared to the current "Zen 4." The core will feature a larger 48 KB L1D cache, up from the current 32 KB. In terms of core design, it will have an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage will have 6 ALUs, up from the current 4. The floating-point unit will have FP-512 capabilities. One significant announcement is that AMD has increased the maximum number of cores per CCX from 8 to 16. It is unclear whether this means the "Eldora" CCD will have 16 cores or if the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD will be utilizing the TSMC 4 nm EUV node for "Eldora," while the mobile processor based on "Zen 5" may use the more advanced TSMC 3 nm EUV node. The opening slide also provides an interesting way in which AMD describes its CPU core architectures. According to this, "Zen 3" and "Zen 5" are new cores, while "Zen 4" and the future "Zen 6" cores are leveraged cores. "Zen 3" had previously delivered a significant 19% IPC uplift over "Zen 2," which helped AMD dominate the CPU market. Although the estimated 15% IPC gain for "Zen 5" is more conservative, it is still expected to have a significant impact on AMD's competitiveness.

Regarding the "Zen 6" microarchitecture and the "Morpheus" core, AMD anticipates a 10% IPC increase over "Zen 5," new FP16 capabilities for the core, and a maximum core count of 32 in a single CCX. This would mark another significant increase in CPU core counts.

Delving deeper into the "Zen 5" core, AMD introduces an even more advanced branch prediction unit. Branch predictor improvements played a major role in the generational IPC gain of "Zen 4." The new branch predictor comes with zero bubble conditional branches capabilities, improved accuracy, and a larger BTB (branch target buffer). As mentioned earlier, the core will have a larger 48 KB L1D cache and an unspecified larger D-TLB. There will be throughput improvements across the front-end and load/store stages, including dual basic block fetch units, 8-wide op dispatch/rename, Op Fusion, a 50% increase in ALCs, a deeper execution window, a more capable prefetcher, and updates to the CPU core ISA and security. The dedicated L2 cache per core will remain at 1 MB in size.