Intel Showcases Next-Generation Advanced Packaging Technologies

Intel Foundry has unveiled a new video demonstration highlighting its latest advancements in semiconductor packaging, pushing the boundaries of silicon scaling well beyond traditional reticle limits. The demonstration showcases how Intel’s Foveros 3D and EMIB-T interconnect technologies can scale silicon up to 12 times the standard reticle size, enabling the integration of as many as 16 compute dies and 24 HBM5 memory modules within a single package.

Breaking Through Reticle Limits with Foveros 3D and EMIB-T

At the core of Intel’s approach is a sophisticated multi-layer packaging technique. The process begins with base dies manufactured using the advanced 18A-PT node, which incorporates backside power delivery. This innovation not only increases logic density but also enhances reliability. These base dies are designed with SRAM structures inspired by Intel’s “Clearwater Forest” architecture, providing a robust foundation for further integration.

On top of these base dies, compute tiles are built using the cutting-edge 14A and 14A-E process nodes. These tiles feature second-generation RibbonFET transistors and PowerDirect technology, both of which contribute to improved performance and energy efficiency. Foveros Direct 3D technology enables vertical stacking through ultra-fine pitch hybrid bonding, while EMIB-T utilizes through-silicon vias to deliver high-bandwidth connections between chiplets. This combination allows Intel to surpass traditional reticle size limitations and support all current and future HBM standards, including HBM4 and HBM5.

Preparing for the Future of High-Performance Computing

Intel’s advanced packaging roadmap includes ambitious plans for high-power GPU designs. The company envisions a 5,000-watt GPU architecture, made possible by integrated voltage regulators (IVRs) and the Foveros-B packaging variant. Intel aims to deliver these 5 kW GPUs by 2027, targeting demanding applications in artificial intelligence and high-performance computing.

Previous innovations, such as the advanced packaging used in the now-retired “Ponte Vecchio” GPU, have laid the groundwork for upcoming products like the “Jaguar Shores” AI accelerators. As Intel continues to expand its packaging capabilities, the company is positioning itself as a strong competitor to established solutions like TSMC’s CoWoS, attracting increasing interest from external customers seeking advanced, scalable chip packaging technologies.